Quantinuum published a preprint last week demonstrating real-time quantum error correction (QEC) cycles on their H2-1 trapped-ion processor — a result that moves the needle on fault-tolerant computing timelines.
What Was Demonstrated
The team implemented a 7-qubit Steane code logical qubit using H2-1's 56 physical qubits, performing 10 rounds of syndrome measurement and real-time feed-forward correction within a single circuit execution. Crucially, the logical error rate after 10 QEC cycles was lower than the equivalent physical qubit error rate — the break-even point that demonstrates genuine error suppression.
The logical two-qubit gate error rate was measured at 2.8 × 10⁻³, achieved through real-time decoding using a minimum-weight perfect matching (MWPM) decoder running on an on-chip FPGA co-processor. Correction latency was approximately 1.2 ms per syndrome round.
Why This Matters
Most QEC demonstrations to date have been post-hoc — errors are recorded but correction is simulated classically afterward. Real-time correction (feed-forward) is necessary for fault-tolerant computation because logical algorithms cannot pause between syndrome cycles. H2-1's demonstration of real-time feed-forward at 56 qubits with genuine logical error suppression is the most practically significant QEC milestone since Google's 2023 surface code below-threshold result.
The Trapped-Ion Advantage
H2-1's all-to-all connectivity is essential for this result. Steane code syndrome circuits require connectivity between non-neighboring qubits; in superconducting systems with grid topology, this requires SWAP chains that add error. Trapped-ion systems implement these circuits natively.
What's Next
Quantinuum's roadmap targets a 100+ logical qubit system by 2028 using concatenated codes. The H2-1 result validates the physical layer; the challenge now is scaling the decoder and classical control bandwidth alongside qubit count.